The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

Nov. 07, 2023
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Anurag Agrawal, Santa Clara, CA (US);

John Andrew Fingerhut, Cary, NC (US);

Xiaoyan Ding, Lantau Island, HK;

Song Zhang, Beijing, CN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04L 47/628 (2022.01); H04L 45/24 (2022.01); H04L 49/00 (2022.01);
U.S. Cl.
CPC ...
H04L 47/628 (2013.01); H04L 45/24 (2013.01); H04L 49/3063 (2013.01);
Abstract

Examples described herein relate to a network interface device comprising a multi-stage programmable packet processing pipeline circuitry to determine a path to transmit a packet based on relative network traffic transmitted via multiple paths. In some examples, determine a path to transmit a packet is based on Deficit Round Robin (DRR). In some examples, the programmable packet processing pipeline circuitry includes: a first stage to manage two or more paths, wherein a path of the two or more paths of the first stage is associated with two or more child nodes, a second stage to manage two or more paths, wherein a path of the two or more paths of the second stage is associated with two or more child nodes, and at least one child node is associated with the determined path.


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