Digital phase-locked loops (pll) including closed-loop time-to-digital converter (tdc) gain calibration circuits and related methods

Abstract

In a calibrated digital phase-locked-loop (DPLL) circuit, during a normal operating mode, a control value provided to a digitally controlled oscillator (DCO) is updated by a feedback circuit to keep an output clock generated by the DCO synchronized with a reference clock. The feedback circuit includes a time-to-digital converter (TDC) circuit to measure a phase difference as a time interval. In a calibration operating mode of the calibrated DPLL circuit, calibration of a resolution of a time measurement of the time interval measured by the TDC is performed in the feedback circuit while the control value provided to the DCO is kept constant. Calibrating the TDCs in each of the DPLLs in an integrated circuit (IC) to a nominal resolution in this manner improves synchronization of the clock domains. In some examples, the TDC circuit is a Vernier type circuit and calibration sets a delay difference to a nominal resolution.