The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

Nov. 10, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Georgios Dogiamis, Chandler, AZ (US);

Adel A. Elsherbini, Tempe, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/66 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01Q 1/22 (2006.01); H01Q 9/04 (2006.01);
U.S. Cl.
CPC ...
H01L 23/66 (2013.01); H01L 23/5384 (2013.01); H01L 25/0652 (2013.01); H01L 25/50 (2013.01); H01Q 1/2283 (2013.01); H01Q 9/0407 (2013.01);
Abstract

A microelectronic assembly is provided comprising: a first IC die in a first layer comprising an array of radio frequency (RF) patch antennas on a side opposite to a second layer; a second IC die in the second layer between the first layer and a third layer; and a third IC die in the third layer. The first IC die comprises RF and analog circuitry, the first IC die is part of an array of IC dies having similar size and circuitry as the first IC die, the second layer and the third layer comprise a dielectric with through-dielectric vias (TDVs) therein surrounding the second IC die and the third IC die, respectively, and an interface between adjacent layers comprises interconnects having a pitch of 10 micrometers between adjacent interconnects.


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