The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

Dec. 02, 2022
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Bogdan Cezar Zota, Rueschlikon, CH;

Bernd W. Gotsmann, Horgen, CH;

Heinz Schmid, Horgen, CH;

Alan Molinari, Kilchberg, CH;

Lorenzo Rocchino, Zurich, CH;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/532 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H01L 23/53266 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01);
Abstract

Described is an integrated circuit device comprising one or more interconnects. Each interconnect of the one or more interconnects can be structured as a stack of layers including distinct topological layers, where each of the distinct topological layers can be a layer of topological material. Any two successive layers of the distinct topological layers can be separated by one or more interfaces, each forming a boundary between two consecutive layers of the stack, where the two consecutive layers can be engineered to preserve topologically protected surface states of each of the any two successive layers of the distinct topological layers.


Find Patent Forward Citations

Loading…