The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

Jul. 20, 2022
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Werner Schustereder, Villach, AT;

Ravi Keshav Joshi, Klagenfurt, AT;

Hans-Joachim Schulze, Taufkirchen, DE;

Ralf Siemieniec, Villach, AT;

Axel Koenig, Villach, AT;

Assignee:

INFINEON TECHNOLOGIES AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/04 (2006.01); H10D 62/832 (2025.01); H10D 64/62 (2025.01);
U.S. Cl.
CPC ...
H01L 21/0485 (2013.01); H10D 62/8325 (2025.01); H10D 64/62 (2025.01);
Abstract

The present disclosure relates to methods of manufacturing Ohmic contacts on a silicon carbide (SiC) substrate including providing a 4H—SiC or 6H—SiC substrate, implanting dopants into a surface region of the 4H—SiC or 6H—SiC substrate, annealing the implanted surface regions to form a 3C—SiC layer, and depositing a metal layer on the 3C—SiC layer. An implanting sequence of the implantation of dopants includes a plurality of plasma deposition acts with implantation energy levels including at least two different implantation energy levels. The implantation energy levels and one or more implantation doses of the plurality of plasma deposition acts are selected to form a 3C—SiC layer in the surface region of the 4H—SiC or 6H—SiC substrate during the annealing act. A method of manufacturing a semiconductor device having a structure including at least three layers including a 4H—SiC or 6H—SiC layer, a 3C—SiC layer, and a metal layer, by applying one or more of the techniques described herein, and semiconductor devices obtained with one or more of the techniques described herein are described.


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