Hardware accelerator for computing an algebraic function

Abstract

A multi-thread processor computes a function requiring only modular additions and multiplications. Memories store constants, multi-bit elements, and multiple instruction sets. A multiplier receives first and second multiplier operands, generates their product, which is fed to an adder as a first operand and added to a second adder operand, the sum being stored in an accumulator memory. Each instruction set is executed on a successive clock, and includes instructions for defining respective addresses in the memories from which constants, elements and sums are to be accessed. A scheduler maintains a schedule of threads executable by the processor in parallel, and is configured on each successive clock to cycle through the threads and initiate a first available thread. Selectors responsive to instructions received from the program memory select the required multiplier and adder operands. A multi-core system executes multiple parallel threads on multiple processors allowing complex functions to be computed efficiently.