The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2025

Filed:

Jan. 12, 2024
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Abhijeet Ashok Chachad, Plano, TX (US);

Timothy David Anderson, University City, TX (US);

David Matthew Thompson, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/448 (2018.01); G06F 9/48 (2006.01); G06F 9/54 (2006.01); G06F 11/30 (2006.01); G06F 12/0804 (2016.01); G06F 12/0811 (2016.01); G06F 12/0813 (2016.01); G06F 12/0817 (2016.01); G06F 12/0831 (2016.01); G06F 12/0855 (2016.01); G06F 12/0871 (2016.01); G06F 12/0888 (2016.01); G06F 12/0891 (2016.01); G06F 12/12 (2016.01); G06F 12/121 (2016.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 9/467 (2013.01); G06F 9/30047 (2013.01); G06F 9/30079 (2013.01); G06F 9/30098 (2013.01); G06F 9/30101 (2013.01); G06F 9/30189 (2013.01); G06F 9/3867 (2013.01); G06F 9/4498 (2018.02); G06F 9/4881 (2013.01); G06F 9/544 (2013.01); G06F 11/3037 (2013.01); G06F 12/0811 (2013.01); G06F 12/0813 (2013.01); G06F 12/0824 (2013.01); G06F 12/0828 (2013.01); G06F 12/0831 (2013.01); G06F 12/0855 (2013.01); G06F 12/0871 (2013.01); G06F 12/0888 (2013.01); G06F 12/0891 (2013.01); G06F 12/12 (2013.01); G06F 13/1668 (2013.01); G06F 12/0804 (2013.01); G06F 12/121 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/621 (2013.01);
Abstract

An apparatus includes a CPU core, a first cache subsystem coupled to the CPU core, and a second memory coupled to the cache subsystem. The first cache subsystem includes a configuration register, a first memory, and a controller. The controller is configured to: receive a request directed to an address in the second memory and, in response to the configuration register having a first value, operate in a non-caching mode. In the non-caching mode, the controller is configured to provide the request to the second memory without caching data returned by the request in the first memory. In response to the configuration register having a second value, the controller is configured to operate in a caching mode. In the caching mode the controller is configured to provide the request to the second memory and cache data returned by the request in the first memory.


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