The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 28, 2025
Filed:
Feb. 04, 2022
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventor:
Kayoko Shibata, Tokyo, JP;
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 23/50 (2006.01); H01L 23/522 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H10D 89/10 (2025.01);
U.S. Cl.
CPC ...
H01L 23/5286 (2013.01); H01L 23/481 (2013.01); H01L 25/0652 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06544 (2013.01);
Abstract
Apparatuses of overlay measurement are disclosed. An example apparatus includes: a memory array region; a peripheral region adjacent to the memory array region; a plurality of power vias in the peripheral region that provide one or more power supply voltages; and one or more wirings in the peripheral region. The one or more wirings are disposed adjacent to the memory array region. One or more power vias of the plurality of power vias are disposed through a wiring of the one or more wirings.