The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2025

Filed:

Nov. 06, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Andre Xian Ming Chang, Seattle, WA (US);

Aliasger Tayeb Zaidy, Seattle, WA (US);

Marko Vitez, Trieste, IT;

Michael Cody Glapa, Washington, DC (US);

Abhishek Chaurasia, Seattle, WA (US);

Eugenio Culurciello, West Lafayette, IN (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06N 3/08 (2023.01); G06F 8/41 (2018.01); G06N 3/04 (2023.01);
U.S. Cl.
CPC ...
G06N 3/08 (2013.01); G06F 8/443 (2013.01); G06N 3/04 (2013.01);
Abstract

Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory (RAM). A compiler has an artificial neural network configured to identify an optimized compilation option for an artificial neural network to be compiled by the compiler and/or for a hardware platform of Deep Learning Accelerators. The artificial neural network of the compiler can be trained via machine learning to identify the optimized compilation option based on the features of the artificial neural network to be compiled and/or features of the hardware platform on which the compiler output will be executed.


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