The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2025

Filed:

Mar. 31, 2022
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Shubham Jain, Elmsford, NY (US);

Hsinyu Tsai, San Jose, CA (US);

Geoffrey Burr, Cupertino, CA (US);

Milos Stanisavljevic, Adliswil, CH;

Pritish Narayanan, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/065 (2023.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06N 3/065 (2023.01); G06F 9/3001 (2013.01); G06F 9/30036 (2013.01); G06F 9/3877 (2013.01);
Abstract

Embodiments disclosed herein include a compute in-memory (CIM) accelerator architecture for deep neural network (DNN). The CIM accelerator architecture may include a first analog fabric engine having a plurality of compute in-memory (CIM) analog tiles. Each CIM analog tile may be configured to store a matrix of weight operands producing a vector of outputs from a vector of inputs, and perform in-memory computations. The first analog fabric may also include a plurality of compute cores. Each CIM analog tile and each compute core may include a microcontroller configured to execute a set of instructions. The first analog fabric may also include on-chip interconnects communicatively connecting all CIM analog tiles in the plurality of CIM analog tile to the compute cores.


Find Patent Forward Citations

Loading…