The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2025

Filed:

Oct. 06, 2023
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Anatoly Gelman, San Diego, CA (US);

Michael James Smith, Vancouver, CA;

James Cheng-Huan Wu, Vancouver, CA;

Olivier Alavoine, San Diego, CA (US);

Amit Aneja, Chandler, AZ (US);

Assignee:

Qualcomm Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/343 (2020.01); G01R 31/3185 (2006.01); G06F 1/3228 (2019.01); G06F 1/3296 (2019.01); G06F 11/27 (2006.01); G06F 30/327 (2020.01); G06F 119/06 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/343 (2020.01); G01R 31/318566 (2013.01); G06F 1/3228 (2013.01); G06F 1/3296 (2013.01); G06F 11/27 (2013.01); G06F 30/327 (2020.01); G06F 2119/06 (2020.01); G06F 2119/12 (2020.01);
Abstract

Aspects relate to monitoring timing margin of logic paths and its degradation through an integrated circuit. In one example an integrated circuit has a logic path formed in the integrated circuit. A monitor circuit is formed in the integrated circuit near the logic path and configured to monitor a condition of the logic path and to generate a diagnostic code sequence to indicate the condition of the logic path over time. A monitor controller is configured to receive diagnostic codes of the diagnostic code sequence, to determine a condition of the integrated circuit based on the diagnostic code sequence, and to initiate a remedial action in response to the condition of the integrated circuit.


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