The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 28, 2025
Filed:
Mar. 24, 2022
Intel Corporation, Santa Clara, CA (US);
Ravi L. Sahita, Portland, OR (US);
Kunal Mehta, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An apparatus provides a processor configured to execute instructions of a hypervisor to provide hypervisor-managed linear address translation (HLAT) with integrity protection. The processor is to execute the instructions to select a first key identifier for a first virtual machine to run on the hypervisor, invoke a first platform configuration instruction to configure the first key identifier in the processor including generating an encryption key for the first key identifier and setting an integrity mode for the first key identifier, instantiate the first virtual machine including a first guest kernel, the first guest kernel to allocate a plurality of HLAT paging structures to be used to translate a guest virtual address to a guest physical address of a first memory page allocated for the first virtual machine, mark the plurality of HLAT paging structures with read-only permission, and assign the first key identifier to the first memory page.