The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2025

Filed:

Nov. 23, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jaegwon Jang, Hwaseong-si, KR;

Seokhyun Lee, Hwaseong-si, KR;

Kyoung Lim Suk, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10F 39/00 (2025.01); H01L 23/31 (2006.01); H01L 23/485 (2006.01); H01L 25/065 (2023.01); H10F 39/12 (2025.01);
U.S. Cl.
CPC ...
H10F 39/809 (2025.01); H01L 23/3157 (2013.01); H01L 23/485 (2013.01); H01L 25/0657 (2013.01); H10F 39/026 (2025.01); H10F 39/804 (2025.01); H10F 39/811 (2025.01); H10F 39/199 (2025.01);
Abstract

A semiconductor package includes a first redistribution layer, a first semiconductor chip on the first redistribution layer, a molding layer covering the first semiconductor chip, metal pillars around the first semiconductor chip and connected to the first redistribution layer, a second redistribution layer on the molding layer and connected to the metal pillars, and a second semiconductor chip on the second redistribution layer. The metal pillars extend through the molding layer. When viewed in plan, the second semiconductor chip overlaps the first semiconductor chip and the metal pillars. A method of manufacturing the semiconductor package obtains a wafer map from a first substrate that includes a plurality of first semiconductor chips and uses the wafer map in selectively stacking second semiconductor chips on the first semiconductor chips.


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