The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2025

Filed:

Nov. 20, 2020
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Manabu Sato, Oyama, JP;

Susumu Kawashima, Atsugi, JP;

Koji Kusunoki, Isehara, JP;

Hidenori Mori, Kawachi, JP;

Hironori Matsumoto, Tochigi, JP;

Daisuke Kurosaki, Utsunomiya, JP;

Masami Jintyou, Shimotsuga, JP;

Masataka Nakada, Tochigi, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 86/40 (2025.01); H10D 30/67 (2025.01); H10D 86/60 (2025.01); H10K 59/12 (2023.01);
U.S. Cl.
CPC ...
H10D 86/423 (2025.01); H10D 30/6733 (2025.01); H10D 86/441 (2025.01); H10D 86/471 (2025.01); H10D 86/481 (2025.01); H10D 86/60 (2025.01); H10K 59/12 (2023.02);
Abstract

A semiconductor device with high reliability is provided. The semiconductor device includes a first transistor, a second transistor, a capacitor, and first to fourth wirings. The first transistor includes a first gate and a second gate, and one of a source and a drain of the first transistor is connected to the first wiring and the second gate, and the other of the source and the drain is connected to one of a source and a drain of the second transistor and one electrode of the capacitor. A gate of the second transistor is connected to the other electrode of the capacitor, and the other of the source and the drain of the second transistor is electrically connected to the second wiring. The first wiring is supplied with a first potential, and the second wiring is supplied with a second potential and a third potential alternately. The third wiring is connected to the first gate and supplied with a first signal. The fourth wiring is connected to the gate of the second transistor and supplied with a second signal obtained by inverting the first signal.


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