The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2025

Filed:

Jan. 18, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Tzu-Ging Lin, Kaohsiung, TW;

Shun-Hui Yang, Jungli, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 84/0151 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/038 (2025.01);
Abstract

Provided are multi-gate devices and methods for fabricating such devices. An exemplary method includes forming gate structures over a semiconductor material, wherein the gate structures include a long channel (LC) gate structure and a short channel (SC) gate structure; forming a patterned mask over the semiconductor material, wherein the LC gate structure and the SC gate structure are not covered by the patterned mask; and performing an etch process on the LC gate structure and on the SC gate structure through the patterned mask to remove the LC gate structure and the SC gate structure, wherein removal of the LC gate structure forms a deep trench in the semiconductor substrate having a first depth, and wherein removal of the SC gate structure forms a shallow trench in the semiconductor substrate having a second depth less than the first depth.


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