The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2025

Filed:

Jun. 03, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Wei Cheng Wu, Zhubei, TW;

Alexander Kalnitsky, San Francisco, CA (US);

Chien-Hung Chang, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/35 (2023.01); H01L 21/033 (2006.01); H10B 43/50 (2023.01); H10D 30/69 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10B 43/35 (2023.02); H01L 21/0337 (2013.01); H10B 43/50 (2023.02); H10D 30/699 (2025.01); H10D 62/115 (2025.01); H10D 64/037 (2025.01);
Abstract

Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC is manufactured by forming a plurality of deep trenches including an isolation trench and a logic device trench from a top surface of a substrate, filling an isolation material in the isolation trench and the logic device trench, removing the isolation material from the logic device trench, forming a first logic device by filling a first logic gate dielectric and a first logic gate electrode in the logic device trench, and forming first and second source/drain regions in the substrate on opposite sides of the logic device trench. The isolation material is kept in the isolation trench to form an isolation structure.


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