The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2025

Filed:

Dec. 01, 2023
Applicant:

Stmicroelectronics International N.v., Geneva, CH;

Inventors:

Carlo Curina, Bareggio, IT;

Valerio Bendotti, Vilminore di Scalve, IT;

Nicola De Campo, Cura Carpignano, IT;

Valerio Gennari Santori, Milan, IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/22 (2006.01); H03K 5/24 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
H03K 17/223 (2013.01); H03K 5/2454 (2013.01); H03K 5/2481 (2013.01); H03K 19/018514 (2013.01);
Abstract

A receiver circuit receives a differential signal that includes positive and negative spikes, and produces an output signal as a function of the differential signal. A first comparator produces an intermediate set signal that includes a pulse at each positive spike of the differential signal, and a second comparator produces an intermediate reset signal that includes a pulse at each negative spike of the differential signal. A logic circuit detects whether the digital signal switches between a first value and a second value, and whether the intermediate reset signal and the intermediate set signal include pulses lasting longer than a threshold. The logic produces a set correction signal and a reset correction signal. The logic circuit produces a corrected set signal and a corrected reset signal. An output circuit produces an output signal based on the corrected set signal and the corrected reset signal.


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