The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2025

Filed:

Dec. 22, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Kwanyeob Chae, Suwon-si, KR;

Chulwoo Kim, Seoul, KR;

Yoonjae Choi, Seoul, KR;

Kyeongkeun Kang, Suwon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/012 (2006.01); H03K 17/687 (2006.01);
U.S. Cl.
CPC ...
H03K 3/012 (2013.01); H03K 17/6872 (2013.01);
Abstract

A semiconductor device is provided. The semiconductor device includes: an equalizer circuit configured to output a first control signal corresponding to a first bit of original two-bit data and a second control signal corresponding to a second bit of the original two-bit data; and a driver circuit including a plurality of pull-up transistors connected between an output node and a first power node configured to provide a first power supply voltage, and a plurality of pull-down transistors connected between the output node and a second power node configured to provide a second power supply voltage, wherein the second power supply voltage is lower than the first power supply voltage, and the driver circuit is connected to the equalizer circuit in series. The plurality of pull-up transistors includes a first pull-up transistor and a second pull-up transistor connected to each other in parallel, between the first power node and the output node, and a third pull-up transistor and a fourth pull-up transistor connected to each other in series, between the first power node and the output node.


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