The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2025

Filed:

Oct. 28, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Doyoung Jang, Suwon-si, KR;

Eunsu Lee, Asan-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49816 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 23/49866 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 25/105 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/15331 (2013.01);
Abstract

A semiconductor package includes a first package substrate, a semiconductor chip on the first package substrate, a second package substrate over the first package substrate and the semiconductor chip, and a plurality of core structures and a plurality of solder balls. The core structures and the solder balls are between the first package substrate and the second package substrate, a first portion of the plurality of core structures and the plurality of solder balls are apart from the semiconductor chip in a first dimension direction, and a second portion of the plurality of core structures and the plurality of solder balls are apart from the semiconductor chip in a second dimension direction that is different than the first dimension direction. The semiconductor package includes a plurality of strip guides between the semiconductor chip and the plurality of core structures, and in parallel with a periphery of the semiconductor chip.


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