The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 21, 2025
Filed:
May. 27, 2022
Changxin Memory Technologies, Inc., Hefei, CN;
Beijing Superstring Academy of Memory Technology, Beijing, CN;
Xiaoguang Wang, Hefei, CN;
Huihui Li, Hefei, CN;
Qiang Zhang, Hefei, CN;
Shan Wang, Hefei, CN;
Minmin Wu, Hefei, CN;
CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei, CN;
BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY, Beijing, CN;
Abstract
Embodiments relate to the field of semiconductor manufacturing technology, and more particularly, to a method for fabricating a semiconductor structure and a semiconductor structure. The method for fabricating a semiconductor structure provided by the embodiments of the present disclosure includes: providing a substrate including an array region and a peripheral region; forming a first mask layer covering the array region and the peripheral region on the substrate; forming a first device structure pattern on the first mask layer, and then forming a second device structure pattern on the first mask layer; and etching the substrate by using the first device structure pattern and the second device structure pattern as mask layer to form a peripheral region structure and an array region structure synchronously on the substrate. Technological processes are simplified, fabrication difficulties are reduced, and production efficiency is improved.