The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2025

Filed:

Jun. 01, 2022
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventors:

Kyohei Akiyoshi, Tokyo, JP;

Atsushi Yoshida, Tokyo, JP;

Yosuke Nakanishi, Tokyo, JP;

Shinichiro Katsuki, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/04 (2006.01); H10D 12/01 (2025.01); H10D 62/832 (2025.01); H10D 64/01 (2025.01); H01L 21/311 (2006.01); H10D 30/66 (2025.01);
U.S. Cl.
CPC ...
H01L 21/049 (2013.01); H10D 12/031 (2025.01); H10D 62/8325 (2025.01); H10D 64/01 (2025.01); H01L 21/31111 (2013.01); H10D 30/66 (2025.01);
Abstract

Provided is a method of manufacturing a semiconductor device capable of suppressing variation in thickness of oxide films among a plurality of SiC wafers. Forming first inorganic films on lower surfaces of a plurality of SiC wafer, and then performing etching of the plurality of SiC wafers so that 750 nm or more of the first inorganic film is left in thickness, and then forming oxide films on upper surfaces of the plurality of SiC wafers by performing thermal oxidation treatment in a state in which a first SiC wafer of the plurality of SiC wafers is placed directly below any one of at least one wafer, including at least one of a dummy wafer and a monitor wafer, and a second SiC wafer of the plurality of SiC wafers is placed directly below a third SiC wafer of the plurality of SiC wafers.


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