The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 21, 2025
Filed:
May. 24, 2023
Samsung Electronics Co., Ltd., Suwon-si, KR;
Inho Kang, Suwon-si, KR;
Daeseok Byeon, Suwon-si, KR;
Beakhyung Cho, Suwon-si, KR;
Min-Hwi Kim, Suwon-si, KR;
Yongsung Cho, Suwon-si, KR;
Gyosoo Choo, Suwon-si, KR;
SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;
Abstract
Provided is a non-volatile memory device including a page buffer circuit having a multi-stage structure, wherein a stage of the multi-stage structure includes a high voltage region, a first low voltage region, and a second low voltage region. The high voltage region includes a first high voltage transistor connected to one of first to sixth bit lines and a second high voltage transistor connected to one of seventh to twelfth bit lines, the first low voltage region includes a first transistor connected to the first high voltage transistor, and the second low voltage region includes a second transistor connected to the second high voltage transistor. Each of the first low voltage region and the second low voltage regions has a first width corresponding to a pitch of six bit lines, and the high voltage region has a second width corresponding to a pitch of twelve bit lines.