The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2025

Filed:

Nov. 24, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sangeeta Ghangam Manepalli, Chandler, AZ (US);

Philippe Lecluse, Braine l'Alleud, BE;

Bart Plackle, Molenstede, BE;

Kurt Herremans, Hasselt, BE;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 5/00 (2006.01); G09G 3/36 (2006.01); G09G 5/12 (2006.01); G09G 5/18 (2006.01);
U.S. Cl.
CPC ...
G09G 5/001 (2013.01); G09G 3/3618 (2013.01); G09G 5/12 (2013.01); G09G 5/18 (2013.01); G09G 2310/08 (2013.01); G09G 2360/18 (2013.01);
Abstract

In multi-display systems, such as video walls, comprising a control computing system providing content to multiple display computing systems driving a plurality of displays, the refresh rates of the displays can drift over time. This drift can introduce display artifacts, which can make for an unpleasant viewing experience. To counteract display refresh drift, a control system periodically compares display refresh timestamps of the individual display systems to a reference display refresh timestamp of a reference display system. If the difference exceeds a threshold, the control system determines clock adjustment information that is sent to the display system exhibiting drift. The display system utilizes the clock adjustment information to adjust the frequency of a display system clock, which can be done by writing the clock adjustment information to registers that control the behavior of a phase-locked loop that generates the clock used by display refresh circuitry.


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