The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2025

Filed:

Jun. 02, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Nabeel Meeramohideen Mohamed, Round Rock, TX (US);

Steven Andrew Moyer, Round Rock, TX (US);

David Andrew Roberts, Wellesley, MA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0611 (2013.01); G06F 3/0653 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 2212/7207 (2013.01);
Abstract

Methods, systems, and devices for access heatmap implementations at a host device are described. A host device may leverage access operation monitoring that is performed at a memory device, including various examples of signaling and management of monitoring configurations. For example, a memory device may maintain a storage location for tracking access operation occurrence, for which access operations of a given address may be mapped to multiple fields, and for which each field may be associated with access operations of a respective subset of the addresses. In some examples, such registers may be configured or accessed based on indications (e.g., commands, requests) from a host device, which may support dynamic access operation monitoring that is responsive to various operating conditions. In some examples, the host device may perform evaluations based on such minimum values associated with respective addresses to determine a distribution of data across various portions of memory.


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