The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2025

Filed:

Sep. 24, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Francesc Guim Bernat, Barcelona, ES;

Karthik Kumar, Chandler, AZ (US);

Thomas Willhalm, Sandhausen, DE;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 67/1097 (2022.01); G06F 12/0817 (2016.01); G06F 13/16 (2006.01); G06F 13/36 (2006.01);
U.S. Cl.
CPC ...
H04L 67/1097 (2013.01); G06F 12/0828 (2013.01); G06F 13/1668 (2013.01); G06F 13/36 (2013.01); G06F 2212/621 (2013.01); G06F 2213/40 (2013.01);
Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed that reduce latency and bandwidth consumption when sharing memory across a distributed coherent Edge computing system. The distributed coherent Edge computing system disclosed herein configures a compute express link (CXL) endpoint to share data between memories across an Edge platform. The CXL endpoint configures coherent memory domain(s) of memory addresses, which are initialized from an Edge device connected to the Edge platform. The CXL endpoint also configures coherency rule(s) for the coherent memory domain(s). The CXL endpoint is implemented to snoop the Edge platform in response to read and write requests from the Edge device. The CXL endpoint selectively snoops memory addresses within the coherent memory domain(s) that are defined as coherent based on the coherency rule(s).


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