The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2025

Filed:

Mar. 12, 2024
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Jui-Che Tsai, Tainan, TW;

Shih-Lien Linus Lu, Hsinchu, TW;

Cheng Hung Lee, Hsinchu, TW;

Chia-En Huang, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 9/32 (2006.01); G11C 7/06 (2006.01); G11C 11/4091 (2006.01); H04L 9/08 (2006.01);
U.S. Cl.
CPC ...
H04L 9/3278 (2013.01); G11C 7/06 (2013.01); G11C 11/4091 (2013.01); H04L 9/0861 (2013.01);
Abstract

Disclosed is an input/output circuit for a physical unclonable function generator circuit. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, and at least one input/output (I/O) circuit each coupled to at least two neighboring columns of the PUF cell array, wherein the at least one I/O circuit each comprises a sense amplifier (SA) with no cross-coupled pair of transistors, wherein the SA comprises two cross-coupled inverters with no access transistor and a SA enable transistor, and wherein the at least one I/O circuit each is configured to access and determine logical states of at least two bit cells in the at least two neighboring columns; and based on the determined logical states of the plurality of bit cells, to generate a PUF signature.


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