The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 14, 2025
Filed:
Jul. 20, 2022
Applicant:
United Microelectronics Corp., Hsin-Chu, TW;
Inventors:
Wen-Wen Zhang, Changhua County, TW;
Ming-Chou Lu, Pingtung County, TW;
Kun-Chen Ho, Tainan, TW;
Dien-Yang Lu, Kaohsiung, TW;
Chun-Lung Chen, Tainan, TW;
Chung-Yi Chiu, Tainan, TW;
Assignee:
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 23/528 (2006.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/31116 (2013.01); H01L 21/7682 (2013.01); H01L 21/76832 (2013.01); H01L 23/528 (2013.01); H10D 64/017 (2025.01);
Abstract
A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming a contact etch stop layer (CESL) on the gate structure, forming an interlayer dielectric (ILD) layer on the CESL, forming a contact plug in the ILD layer and adjacent to the gate structure, forming a first stop layer on the ILD layer, and removing the first stop layer and the ILD layer around the gate structure to form an air gap exposing the CESL.