The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2025

Filed:

Jun. 09, 2022
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventors:

Michael J. Seddon, Gilbert, AZ (US);

Francis J. Carney, Mesa, AZ (US);

Eiji Kurose, Oizumi-machi, JP;

Chee Hiong Chew, Seremban, MY;

Soon Wei Wang, Seremban, MY;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/302 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/12 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 21/302 (2013.01); H01L 21/48 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 21/78 (2013.01); H01L 23/12 (2013.01); H01L 23/3185 (2013.01); H01L 24/04 (2013.01); H01L 24/26 (2013.01); H01L 2224/94 (2013.01);
Abstract

Implementations of a silicon-in-insulator (SOI) semiconductor die may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be included through a silicon layer coupled to a insulative layer.


Find Patent Forward Citations

Loading…