Memory device having asymmetric page buffer array architecture

Abstract

Memory devices having an asymmetric page buffer array architecture are provided. The memory device includes a memory cell array in which each of plural memory planes is included in a cell array structure, and a row decoder array and a page buffer array included in a peripheral circuit structure vertically overlap the cell array structure. The row decoder array is buried in a region vertically overlapping a word line step region of the cell array structure and a partial region of a memory cell array adjacent to the word line step region. In the page buffer array, bit lines of a partial region of the memory cell array in which the row decoder array is buried are connected to a first page buffer array, and bit lines not included in the partial region are connected to a second page buffer array.