The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2025

Filed:

Dec. 28, 2020
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Kazuki Tsuda, Kanagawa, JP;

Hiromichi Godo, Kanagawa, JP;

Satoru Ohshita, Kanagawa, JP;

Hitoshi Kunitake, Kanagawa, JP;

Satoru Okamoto, Kanagawa, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/35 (2023.01); G11C 16/04 (2006.01); H01L 23/00 (2006.01); H01L 23/528 (2006.01); H10B 41/30 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10D 30/67 (2025.01); H10B 41/10 (2023.01); H10B 69/00 (2023.01);
U.S. Cl.
CPC ...
G11C 16/0483 (2013.01); H01L 23/5283 (2013.01); H01L 24/48 (2013.01); H10B 41/30 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10D 30/6755 (2025.01); H01L 2224/73265 (2013.01); H01L 2924/00 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/181 (2013.01); H10B 41/10 (2023.02); H10B 69/00 (2023.02);
Abstract

A highly reliable memory device is provided. The memory device includes a first conductor, a second conductor above the first conductor, a third conductor above the second conductor, a fourth conductor above the third conductor, a fifth conductor above the fourth conductor, a sixth conductor above the fifth conductor, a seventh conductor, a first insulator, a second insulator, a first semiconductor, and a second semiconductor. At least third conductor and the fourth conductor have an opening. The first insulator, the first semiconductor, the second insulator, and the second semiconductor are provided in this order on an inner surface of the opening. The seventh conductor is provided between the first semiconductor and the second insulator in a region between the third conductor and the second insulator. The first semiconductor is electrically connected to the second conductor and the fifth conductor. The second semiconductor is electrically connected to the first conductor and the sixth conductor.


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