The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2025

Filed:

Dec. 04, 2023
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Siddhartha Chhabra, Portland, OR (US);

David M. Durham, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/00 (2013.01); G06F 12/14 (2006.01); G06F 21/52 (2013.01); G06F 21/53 (2013.01); G06F 21/60 (2013.01); G06F 21/64 (2013.01); G06F 21/71 (2013.01); G06F 21/72 (2013.01); H04L 9/06 (2006.01); H04L 9/08 (2006.01); H04L 9/14 (2006.01); H04L 9/32 (2006.01); H04L 9/40 (2022.01);
U.S. Cl.
CPC ...
G06F 12/1408 (2013.01); G06F 21/52 (2013.01); G06F 21/53 (2013.01); G06F 21/602 (2013.01); G06F 21/64 (2013.01); G06F 21/71 (2013.01); G06F 21/72 (2013.01); H04L 9/0631 (2013.01); H04L 9/0637 (2013.01); H04L 9/0894 (2013.01); H04L 9/14 (2013.01); H04L 9/3273 (2013.01); H04L 63/0428 (2013.01); H04L 63/061 (2013.01); H04L 63/126 (2013.01); H04L 63/1466 (2013.01); H04L 2463/062 (2013.01);
Abstract

In one embodiment, a multi-tenant computing system includes a processor including a plurality of cores on which agents of tenants of the multi-tenant computing system are to execute, a configuration storage, and a memory execution circuit. The configuration storage includes a first configuration register to store configuration information associated with the memory execution circuit. The first configuration register is to store a mode identifier to identify a mode of operation of the memory execution circuit. The memory execution circuit, in a first mode of operation, is to receive encrypted data of a first tenant, the encrypted data encrypted by the first tenant, generate an integrity value for the encrypted data, and send the encrypted data and the integrity value to a memory, the integrity value not visible to the software of the multi-tenant computing system. Other embodiments are described and claimed.


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