The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 14, 2025
Filed:
Dec. 22, 2021
Method and apparatus for high-performance page-fault handling for multi-tenant scalable accelerators
Intel Corporation, Santa Clara, CA (US);
Utkarsh Y. Kakaiya, Folsom, CA (US);
Philip Lantz, Cornelius, OR (US);
Sanjay Kumar, Hillsboro, OR (US);
Rajesh Sankaran, Portland, OR (US);
Narayan Ranganathan, Banglore, IN;
Saurabh Gayen, Portland, OR (US);
Dhananjay Joshi, Portland, OR (US);
Nikhil P. Rao, Bengaluru, IN;
Intel Corporation, Santa Clara, CA (US);
Abstract
Apparatus and method for high-performance page fault handling. For example, one embodiment of an apparatus comprises: one or more accelerator engines to process work descriptors submitted by clients to a plurality of work queues; fault processing hardware logic associated with the one or more accelerator engines, the fault processing hardware logic to implement a specified page fault handling mode for each work queue of the plurality of work queues, the page fault handling modes including a first page fault handling mode and a second page fault handling mode.