The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2025

Filed:

Jul. 22, 2022
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Quan Zhang, Wuhan, CN;

Lan Yao, Wuhan, CN;

Jiaji Wu, Wuhan, CN;

Beibei Zhu, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/40 (2023.01); H10B 41/27 (2023.01); H10B 41/40 (2023.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
H10B 43/40 (2023.02); H10B 41/27 (2023.02); H10B 41/40 (2023.02); H10B 43/27 (2023.02);
Abstract

The present disclosure discloses a semiconductor device, a three-dimensional memory and a method for fabricating the semiconductor device. The method includes forming a shallow trench isolation trench in a substrate. The substrate comprises an active region including a source region, a channel region, and a drain region. The shallow trench isolation trench is located on a periphery of the active region of the substrate. The method further comprises forming a bottom isolating layer in a bottom portion of the shallow trench isolation trench, forming a gate structure on a channel region of the substrate, and forming a hard insulating layer in an upper portion of the shallow trench isolation trench and on sidewalls of the active region, such that the hard insulating layer covers a source region and a drain region of the substrate.


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