The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 2025
Filed:
Jan. 31, 2023
Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;
Kuo Hsiung Chen, Hsinchu County, TW;
Ya-Ting Chen, Hsinchu County, TW;
Chun-Ta Chen, Taichung, TW;
Chang Tsung Lin, Taichung, TW;
Shih-Ping Lee, Hsinchu, TW;
Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;
Abstract
A manufacturing method of a semiconductor structure including the following steps is provided. A substrate is provided. A first dielectric layer is formed on the substrate. A first conductive layer is formed in the first dielectric layer. A capping layer is formed on the first dielectric layer and the first conductive layer. The material of the capping layer is nitride. A diffusion barrier layer covering the capping layer is formed. The material of the diffusion barrier layer is silicon-rich oxide (SRO). A second dielectric layer is formed on the diffusion barrier layer. An opening is formed in the second dielectric layer. The opening exposes the diffusion barrier layer. A patterned photoresist layer is formed on the second dielectric layer. A patterning process is performed by using the patterned photoresist layer as a mask to expand the opening and to expose the first conductive layer.