Layout structure of clock tree circuitry and forming method thereof

Abstract

The present disclosure relates to a clock tree layout and a forming method thereof. The clock tree layout includes: a divider module layout, a phase module layout and a wire pattern layer. The divider module layout is configured to receive a first clock signal, and divide the first clock signal, and obtain a plurality of second clock sampling signals phase-associated; the phase module layout includes a first quantity of phase modules disposed in a first preset direction, the phase module is configured to generate a second clock signal based on a correspondingly connected second clock sampling signal, and the phase modules are symmetrically distributed with respect to the divider module layout; the wire pattern layer is configured to electrically connect the phase module and a divider module in the divider module layout; a difference between phases of any two of the second clock signals falls within a preset precision range.