The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2025

Filed:

Feb. 07, 2023
Applicant:

Hefei Reliance Memory Limited, Anhui, CN;

Inventor:

Takeki Ninomiya, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10N 70/20 (2023.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01);
U.S. Cl.
CPC ...
H10N 70/841 (2023.02); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 63/34 (2023.02); H10N 70/883 (2023.02);
Abstract

A memory device includes a memory cell comprising a bottom electrode, a top electrode, and a dielectric layer interposed between the bottom electrode and the top electrode. The bottom electrode has a first width W. The top electrode has a top surface that has a second width Wbetween two edges of the top surface. The memory cell has a first height Hextending from a lower surface of the bottom electrode to the top surface of the top electrode. The memory device further includes a top contact wire coupled to the top electrode. The top contact wire has a top surface that has a third width W, a second height Hat a location between two adjacent memory cells, and a third height Hextending between the top surface of the top contact wire and the insulating layer, where W>W>Wand H>H>H


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