The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 30, 2025
Filed:
May. 24, 2023
Applicant:
Stmicroelectronics, Inc., Coppell, TX (US);
Inventor:
Jocelyne Gimbert, Crolles, FR;
Assignee:
STMICROELECTRONICS, INC., Coppell, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/69 (2025.01); H01L 21/265 (2006.01); H01L 21/324 (2006.01); H01L 21/70 (2006.01); H10D 30/01 (2025.01); H10D 62/832 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 86/00 (2025.01); H10D 86/01 (2025.01); H10D 62/822 (2025.01);
U.S. Cl.
CPC ...
H10D 30/797 (2025.01); H01L 21/26506 (2013.01); H01L 21/26513 (2013.01); H01L 21/324 (2013.01); H01L 21/707 (2013.01); H10D 30/0275 (2025.01); H10D 30/0323 (2025.01); H10D 62/832 (2025.01); H10D 62/8325 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/038 (2025.01); H10D 86/01 (2025.01); H10D 86/201 (2025.01); H10D 30/024 (2025.01); H10D 62/822 (2025.01);
Abstract
Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers.