The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2025

Filed:

May. 27, 2022
Applicants:

Tower Partners Semiconductor Co., Ltd., Uozu, JP;

Tower Semiconductor Ltd., Migdal Haemek, IL;

Inventors:

Hiroshige Hirano, Nara, JP;

Hiroaki Kuriyama, Toyama, JP;

Atsushi Noma, Toyama, JP;

Assignees:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 41/41 (2023.01); G11C 16/14 (2006.01); H10B 41/10 (2023.01); H10B 41/35 (2023.01); H10D 30/68 (2025.01);
U.S. Cl.
CPC ...
H10B 41/41 (2023.02); H10B 41/10 (2023.02); H10B 41/35 (2023.02); H10D 30/684 (2025.01); H10D 30/6892 (2025.01); G11C 16/14 (2013.01);
Abstract

A semiconductor device includes a memory cell on a semiconductor substrate. The memory cell includes a memory element, a first assistance element, and a second assistance element. The memory element includes a source region and a drain region, and a selection gate and a floating gate in series therebetween. The first assistance element includes a first impurity region and a first gate. The second assistance element includes a second impurity region and a second gate. The first and second gates are electrically connected to the floating gate. The second impurity region is connected to a signal line that is connected to the drain region or a signal line that is connected to the selection gate.


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