The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2025

Filed:

Jun. 15, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

David Coyle, Limerick, IE;

Brendan Ryan, Limerick, IE;

Konstantin Ananyev, Naas, IE;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 9/40 (2022.01); H04L 12/28 (2006.01);
U.S. Cl.
CPC ...
H04L 63/101 (2013.01); H04L 12/2801 (2013.01); H04L 63/0236 (2013.01);
Abstract

The present disclosure provides mechanisms to optimize filter processing. Conventional filter processing techniques involve dividing a batch of received data packets into multiple Access Control Lists (ACLs) per filter group, and thus, cannot leverage of optimal ACL processing of large packet batches using the latest processor instruction sets such as 512 bit wide instructions. The filter processing techniques discussed in the present disclosure, some or all rules for a batch of packets are included in a single ACL look-up by including a filter group identifier (ID) in each rule, and also adding the filter group ID to a field of the packet undergoing the ACL look-up. This avoids false matches while also employing a single ACL look-up for an entire batch of packets, regardless of batch-size. The filter processing techniques can be applied to DOCSIS packet processing pipelines and/or other filtering mechanisms.


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