The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 30, 2025
Filed:
Dec. 13, 2022
Globalfoundries U.s. Inc., Malta, NY (US);
Dzung T. Tran, Austin, TX (US);
Deepti A. Pant, Austin, TX (US);
Shibly S. Ahmed, San Jose, CA (US);
GlobalFoundries U.S. Inc., Malta, NY (US);
Abstract
Disclosed is an input buffer with hysteresis-integrated voltage protection devices for avoiding violations of maximum gate-to-source voltage limitations when the maximum input voltage is greater than the maximum gate-to-source voltage limitation. The input buffer includes a chain of transistors including two P-channel FETs (PFETs) and two N-channel FETs (NFETs). The data input to the input buffer controls the gates of the transistors in the chain so the data output from the input buffer at the junction between the PFETs and NFETs is inverted. The input buffer also includes a hysteresis feedback loop to prevent noise-induced switching of the output. The hysteresis feedback loop also includes voltage protection devices integrated therein to avoid maximum gate-to-source violations when the loop results in a hysteresis voltage being fed back into the chain at the source region of a transistor in the chain. Also disclosed is a receiver incorporating the input buffer.