The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2025

Filed:

Apr. 25, 2024
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Po-Chia Lai, Fremont, CA (US);

Meng-Hung Shen, Zhubei, TW;

Chi-Lin Liu, New Taipei, TW;

Stefan Rusu, Sunnyvale, CA (US);

Yan-Hao Chen, Hsin-Chu, TW;

Jerry Chang-Jui Kao, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/3562 (2006.01); H03K 3/012 (2006.01); H03K 3/0233 (2006.01); H03K 3/037 (2006.01); H03K 3/289 (2006.01); H03K 3/356 (2006.01);
U.S. Cl.
CPC ...
H03K 3/012 (2013.01); H03K 3/02332 (2013.01); H03K 3/0372 (2013.01); H03K 3/289 (2013.01); H03K 3/356104 (2013.01); H03K 3/3562 (2013.01); H03K 3/35625 (2013.01);
Abstract

A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.


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