The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2025

Filed:

Sep. 26, 2022
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventor:

Ling-Yi Chuang, Hefei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/311 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 24/32 (2013.01); H01L 21/31133 (2013.01); H01L 21/563 (2013.01); H01L 23/3135 (2013.01); H01L 24/16 (2013.01); H01L 24/29 (2013.01); H01L 24/73 (2013.01); H01L 24/83 (2013.01); H01L 21/565 (2013.01); H01L 24/81 (2013.01); H01L 2224/16258 (2013.01); H01L 2224/29005 (2013.01); H01L 2224/29019 (2013.01); H01L 2224/29076 (2013.01); H01L 2224/29082 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/83203 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1815 (2013.01); H01L 2924/182 (2013.01); H01L 2924/3841 (2013.01);
Abstract

Embodiments disclose a package structure and a fabricating method. The package structure includes: a semiconductor chip; a first non-conductive layer covering a front surface of the semiconductor chip and part of a side wall of the semiconductor chip; a second non-conductive layer positioned on an upper surface of the first non-conductive layer and covering at least part of a side wall of the first non-conductive layer, wherein a melt viscosity of the first non-conductive layer is greater than a melt viscosity of the second non-conductive layer; a substrate; and a solder mask layer positioned on a surface of the substrate, where a first opening is provided in the solder mask layer. The semiconductor chip is flip-chip bonded on the substrate, a surface of the second non-conductive layer away from the first non-conductive layer and a surface of the solder mask layer away from the substrate are bonding surfaces.


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