The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 30, 2025
Filed:
Aug. 19, 2022
Applicant:
Stats Chippac Pte. Ltd., Singapore, SG;
Inventors:
Jinhee Jung, Incheon, KR;
Changoh Kim, Incheon, KR;
Assignee:
STATS ChipPAC Pte. Ltd., Singapore, SG;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/552 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/16 (2023.01);
U.S. Cl.
CPC ...
H01L 23/552 (2013.01); H01L 21/4817 (2013.01); H01L 21/4853 (2013.01); H01L 23/49816 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 25/162 (2013.01); H01L 25/165 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/16151 (2013.01); H01L 2924/1616 (2013.01); H01L 2924/3025 (2013.01);
Abstract
A semiconductor device includes a substrate. An electrical component is disposed over the substrate. An encapsulant is deposited over the electrical component. A vertical interconnect structure is disposed in the encapsulant. A shielding layer is formed over the encapsulant and vertical interconnect structure. A groove is formed in the shielding layer around the vertical interconnect structure. A portion of the shielding layer remains over the vertical interconnect structure as a contact pad.