Method for etching high aspect ratio features within a dielectric using a hard mask stack having multiple hard mask layers

Abstract

Various embodiments of stacked structures, process steps and methods are provided herein for etching high aspect ratio features (e.g., contact holes, vias, trenches, etc.) within one or more underlying layers of a stacked structure to reduce or eliminate problems that occur during conventional high aspect ratio (HAR) etch processes (such as, e.g., bowing, twisting, distortion and wiggling of HAR features etched within the underlying layers). According to one embodiment, a stacked structure in accordance with the present disclosure may include a hard mask (HM) stack formed above and in contact with one or more underlying layers formed on a semiconductor substrate. The HM stack may include at least one silicon-containing hard mask layer formed above a carbon-containing hard mask layer, and may be utilized during one or more etch processes as a combined hard mask for etching HAR features within the one or more underlying layers.