The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 30, 2025

Filed:

Sep. 27, 2023
Applicant:

Rambus Inc., San Jose, CA (US);

Inventor:

Christopher Haywood, Cary, NC (US);

Assignee:

Rambus Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/44 (2006.01); G11C 7/22 (2006.01); G11C 29/00 (2006.01); G11C 29/12 (2006.01); G11C 29/18 (2006.01);
U.S. Cl.
CPC ...
G11C 29/44 (2013.01); G11C 7/22 (2013.01); G11C 29/12015 (2013.01); G11C 29/18 (2013.01); G11C 29/702 (2013.01); G11C 2029/1806 (2013.01);
Abstract

Many error correction schemes fail to correct for double-bit errors and a module must be replaced when these double-bit errors occur repeatedly at the same address. This helps prevent data corruption. In an embodiment, the addresses for one of the memory devices exhibiting a single-bit error (but not the other also exhibiting a single bit error) is transformed before the internal memory arrays are accessed. This has the effect of moving one of the error prone memory cells to a different external (to the module) address such that there is only one error prone bit that is accessed by the previously double-bit error prone address. Thus, a double-bit error at the original address is remapped into two correctable single-bit errors that are at different addresses.


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