The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2025

Filed:

Nov. 18, 2021
Applicant:

Sandisk Technologies, Inc., Milpitas, CA (US);

Inventors:

Takahito Fujita, Yokkaichi, JP;

Kiyokazu Shishido, Yokkaichi, JP;

Hiroyuki Ogawa, Nagoya, JP;

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 84/83 (2025.01); H01L 21/762 (2006.01); H10D 30/01 (2025.01);
U.S. Cl.
CPC ...
H10D 84/83 (2025.01); H01L 21/76224 (2013.01); H10D 30/0227 (2025.01);
Abstract

A semiconductor structure includes at least two field effect transistors. A gate strip including a plurality of gate dielectrics and a gate electrode strip can be formed over a plurality of semiconductor active regions. Deep source/drain regions are formed by implanting dopants into semiconductor active regions without implanting the dopants into inter-electrode regions of a shallow trench isolation structure. The gate strip is divided into gate stacks prior to or after formation of the deep source/drain regions.


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