The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 23, 2025
Filed:
Apr. 20, 2023
National Yang Ming Chiao Tung University, Hsinchu, TW;
Edward Yi Chang, Hsinchu County, TW;
Shih-Chien Liu, Taoyuan, TW;
Chung-Kai Huang, Kaohsiung, TW;
Chia-Hsun Wu, Kaohsiung, TW;
Ping-Cheng Han, Taichung, TW;
Yueh-Chin Lin, New Taipei, TW;
Ting-En Hsieh, Tainan, TW;
National Yang Ming Chiao Tung University, Hsinchu, TW;
Abstract
A method of manufacturing a semiconductor device includes providing a substrate. A channel layer is formed on the substrate. A barrier layer is formed on the channel layer. A source and a drain are formed on the barrier layer. A recess is formed in the barrier layer, in which the recess has a bottom surface, and a portion of the barrier underneath the recess has a thickness. A first dielectric layer is formed to cover the bottom surface of the recess. A charge trapping layer is formed on the first dielectric layer. A first ferroelectric material layer is formed on the charge trapping layer. A second dielectric layer is formed on the first ferroelectric material layer. A second ferroelectric material layer is formed on the second dielectric layer. A gate is formed over the second ferroelectric material layer.