The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2025

Filed:

Jun. 09, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Praveen Joseph, White Plains, NY (US);

Tao Li, Albany, NY (US);

Indira Seshadri, Niskayuna, NY (US);

Ekmini A. De Silva, Slingerlands, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/10 (2025.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/3065 (2006.01); H01L 21/311 (2006.01); H01L 21/762 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 62/115 (2025.01); H01L 21/02164 (2013.01); H01L 21/0217 (2013.01); H01L 21/02225 (2013.01); H01L 21/02238 (2013.01); H01L 21/02252 (2013.01); H01L 21/02381 (2013.01); H01L 21/30604 (2013.01); H01L 21/3065 (2013.01); H01L 21/31116 (2013.01); H01L 21/7624 (2013.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 84/0188 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01);
Abstract

Semiconductor devices and methods of forming the same include forming a first dielectric layer around a semiconductor fin, formed from a first dielectric material, to a target height lower than a height of the semiconductor fin. A second dielectric layer is deposited on the first dielectric layer and is formed from a second dielectric material. A third dielectric layer, formed from the first dielectric material, is formed on the second dielectric layer. The second dielectric layer is etched away to expose a gap on the semiconductor fin. A portion of the semiconductor fin that is exposed in the gap is oxidized to form an isolation layer.


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