The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2025

Filed:

Jan. 21, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Hsinchu, TW;

Inventor:

Chung-Liang Cheng, Changhua, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 63/00 (2023.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/62 (2025.01); H10D 99/00 (2025.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01);
U.S. Cl.
CPC ...
H10B 63/30 (2023.02); H10D 30/6735 (2025.01); H10D 30/6755 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/62 (2025.01); H10D 99/00 (2025.01); H10N 70/011 (2023.02); H10N 70/231 (2023.02); H10N 70/8828 (2023.02);
Abstract

In fabrication of a phase change random access memory (PCRAM), a field effect transistor (FET) logic layer is formed on a first wafer, including a heating FET for each storage cell. The FET logic layer is transferred from the first wafer to a carrier wafer. Thereafter, a storage layer of the PCRAM is formed on the exposed surface of the FET logic layer, including a region of a phase change material for each storage cell that is electrically connected to a channel of the heating FET of the storage cell. The storage layer further includes a second heating transistor for each storage cell that is electrically connected to a channel of the second heating transistor.


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