The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2025

Filed:

Feb. 13, 2023
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Sanh D. Tang, Boise, ID (US);

John K. Zahurak, Eagle, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/23 (2023.01); H10B 41/27 (2023.01); H10B 41/30 (2023.01); H10B 41/35 (2023.01); H10B 43/20 (2023.01); H10B 43/27 (2023.01); H10D 30/68 (2025.01); H10D 30/69 (2025.01); H10D 62/40 (2025.01); H10D 62/834 (2025.01); H10D 64/01 (2025.01); H10D 64/66 (2025.01);
U.S. Cl.
CPC ...
H10B 41/27 (2023.02); H10B 41/30 (2023.02); H10B 41/35 (2023.02); H10B 43/20 (2023.02); H10B 43/27 (2023.02); H10D 30/689 (2025.01); H10D 30/69 (2025.01); H10D 62/40 (2025.01); H10D 62/834 (2025.01); H10D 64/035 (2025.01); H10D 64/037 (2025.01); H10D 64/665 (2025.01); H10D 64/667 (2025.01); H10D 30/693 (2025.01);
Abstract

Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. A portion of the tier of semiconductor material exposed by the opening is processed so that the portion is doped differently than the remaining semiconductor material in the tier. At least substantially all of the remaining semiconductor material of the tier is removed, leaving the differently doped portion of the tier of semiconductor material as a charge storage structure. A tunneling dielectric is formed on a first surface of the charge storage structure and an intergate dielectric is formed on a second surface of the charge storage structure. Additional embodiments are also described.


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